1. Field of the Invention
The invention relates to a method for forming spacers of a semiconductor device, and particularly to a method for forming narrower spacers by using an HDP-CVD scheme accompanied with fewer processes and masks than conventional approaches.
2. Description of the Prior Art
In the currently VLSI (Very-Large-Scale Integration) circuit processes, methods for forming sidewall spacers are important and broadly used technologies because several advantages are offered from applying sidewall spacers. Firstly, sidewall spacers can be employed as masks when implementing lightly doped drain (LDD) layers. Additionally, the sidewall spacers can isolate the conductive layer that the sidewall spacers abut against from conducting current through the spacers to a gate stack which is protect by the spacers. On the other hand, because overetching is one critical disadvantage that usually placing two structures closer together than intended, self-alignment structure is thus required in the modem semiconductor processes for overcoming the overetching problem. Also, the spacers can be used for accommodating misalignment such as the self-aligned contact (SAC) manufacturing. However, there are complicated processes and many masks required for forming a SAC structure in a semiconductor device.
Please refer to FIG. 1, which shows a cross-section representative of a basic structure of SAC. Three isolated gate stacks 102 are formed on a wafer 100, wherein each the gate stack 102 is basically composed of a gate oxide layer (not shown) a polysilicon layer 104, a gate metal layer 106, a cap layer 108, spacers 110, and a cap dielectric layer 112. Tungsten silicide (WSi.sub.x) is a broadly employed material to form the gate metal layer 106 conventionally. The silicide film formed on the polysilicon layer 104, known as a policide structure, have been fabricated to lower the sheet resistance of the polysilicon gates.
Typically, the formation of the above layers, such as the polysilicon layer 104, metal layer 106 and cap layer 108, are sequentially deposited and patterned on the wafer 100. Next, conventionally, the spacer 110 is formed from depositing a silicon dioxide or silicon nitride layer then followed by an anisotropically etch process. Finally, a cap silicon nitride layer can be deposited followed by an anisotropically etch process to fabricate the cap dielectric layer 112. After an internal dielectric layer 114 is deposited and patterned on the wafer 100, a contact 116 is then formed on the wafer 100 through anisotropically etching the internal dielectric layer 114. As noted, the detail structures in the wafer are not shown for simplifying descriptions, and the above two contacts 116 and the internal dielectric layer 114 are used for conducting and protecting purpose, respectively. As known by the skilled persons, the cap dielectric layer 112 is used for self-aligned purpose so as to terminate the formation of the contact 116, which indicates that the compositions of the cap dielectric layer 112 and the internal dielectric layer 114 must have high selectivity. Conventionally, the cap dielectric layer 112 is composed by silicon nitride and the internal dielectric layer 114 is composed by dioxide.
On the other hand, vertical sidewall spacers are typically formed in conventional approaches for achieving spacer length criteria; however, the anisotropically etch process for forming the contact 116 will simultaneously etch portions of the spacers 110, which will decrease the spacer size and thus destroy the gate stack 102. Accordingly, the application of employing the cap dielectric layer 112 can protect the spacers 110 from being overetched, which also implies that the conduction between the metal layer 106 and the contact 116 and be avoided.
Unfortunately, some disadvantages are still offered by the conventional SAC structure. Firstly, the spacers 110 and cap dielectric layer 112 usually occupy large available spaces between two gate stacks 102, which will in turn increase the aspect ratio for following gap filling processes. Some further drawbacks, such as voids, may be arisen in the consecutive gap filling processes due to poor step coverage, for example when depositing the internal dielectric layer 114. Secondly, the required cap layer 108 for protecting the gate stacks 102 will make the whole integration complicated, hard to control, and costly. For example, the composition of the cap layer 108 is usually not the same as those deposition layers under it. Therefore, different processes are required to respectively etch the cap layer 108, metal layer 106 and polysilicon layer 104 accompanied with etchant having high selectivity for avoiding undesired etch results. A need has arisen to disclose a method for forming a spacer with narrower width than conventional approaches, in which the cap dielectric layer used conventionally, can be eliminated for cost-down purpose simultaneously.